Method for producing a pillar-shaped semiconductor device

ABSTRACT

A method for producing a pillar-shaped semiconductor device having a semiconductor pillar on a semiconductor substrate. A first material layer is formed surrounding the semiconductor pillar and the semiconductor substrate is etched using the first material layer as a mask to form a semiconductor-pillar base part under the semiconductor pillar that surrounds the semiconductor pillar in plan view. A second material layer is formed to cover an upper portion of the semiconductor-pillar base part and the first material layer. An oxidation-layer base part is formed at a lower portion of the semiconductor base part by oxidizing the semiconductor substrate and a lower portion of the semiconductor-pillar base part using the second material layer as an oxidation-resistant mask. The semiconductor pillar is within the oxidation-layer base part in plan view, and an upper surface of the oxidation-layer base part is lower than an upper surface of the semiconductor-pillar base part along a vertical direction.

CROSS REFERENCES TO RELATED APPLICATIONS

The present application is a continuation application of U.S. patentapplication Ser. No. 16/277,670, filed Feb. 15, 2019, which is acontinuation of PCT/JP2016/074084, filed Aug. 18, 2016, the entirecontents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to a pillar-shaped semiconductor deviceand a method for producing the pillar-shaped semiconductor device.

Description of the Related Art

In these years, pillar-shaped semiconductor devices havingthree-dimensional structures have come to be used for LSI (Large ScaleIntegration). As such semiconductor devices, SGTs (Surrounding GateTransistors) have been attracting attention because of the highperformance. There has been a demand for a pillar-shaped semiconductordevice that has higher density and higher performance and is produced atlower costs.

Existing planar MOS transistors are formed on the surface layers ofsemiconductor substrates. By contrast, SGTs are formed in pillar-shapedsemiconductors formed on substrates (for example, Japanese UnexaminedPatent Application Publication No. 2-188966; and Hiroshi Takato,Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, FumioHoriguchi, and Fujio Masuoka: IEEE Transaction on Electron Devices, Vol.38, No. 3, pp. 573-578 (1991)). Thus, compared with planar MOStransistors, SGTs enable semiconductor devices having higher performanceand higher density.

FIG. 9 is a schematic structural view of an N-channel SGT. A Si pillar200 of a P or i (intrinsic) conductivity type (hereafter, siliconsemiconductor pillars will be referred to as “Si pillars”) has, in itsupper and lower portions, N⁺ layers 201 a and 201 b one of whichfunctions as a source and the other one of which functions as a drain(hereafter, semiconductor regions containing a donor impurity at a highconcentration will be referred to as “N⁺ layers”). A portion of the Sipillar 200 between the N⁺ layers 201 a and 201 b, which function as asource and a drain, functions as a channel region 202. Around thischannel region 202, a gate insulating layer 203 is formed. Around thisgate insulating layer 203, a gate conductor layer 204 is formed. In theSGT, the N⁺ layers 201 a and 201 b, which function as a source and adrain, the channel region 202, the gate insulating layer 203, and thegate conductor layer 204 are formed along the single Si pillar 200.Thus, in plan view, the area occupied by the SGT corresponds to the areaoccupied by a single source-or-drain N⁺ layer of a planar MOStransistor. As a result, compared with a circuit chip including a planarMOS transistor, an SGT-including circuit chip enables a furtherreduction in the chip size. The on-state current flowing through thechannel region 202 is efficiently controlled with the gate conductorlayer 204 surrounding the Si pillar 200, to thereby achieve highperformance, compared with the planar MOS transistor.

There has been a demand for an SGT that has higher density and higherperformance and is produced at lower costs. In order to increase thedensity of an SGT, a semiconductor pillar may be formed so as to have areduced sectional diameter in plan view. However, since thesemiconductor pillar is elongated and easily damaged, such a reductionin the sectional diameter causes difficulties in the production. Thedifficulties make it difficult to provide an SGT that has higherperformance and is produced at lower costs.

SUMMARY OF THE INVENTION

There has been a demand for a pillar-shaped semiconductor device thathas higher density and higher performance and is produced at lowercosts.

A method for producing a pillar-shaped semiconductor device according toa first aspect of the present invention is

-   -   a method for producing a pillar-shaped semiconductor device        including a pillar-shaped semiconductor including a        semiconductor pillar, first and second impurity regions in        contact with lower and upper portions of the semiconductor        pillar, a gate insulating layer formed so as to surround the        semiconductor pillar between the first and second impurity        regions disposed in a vertical direction, and a gate conductor        layer formed so as to surround the gate insulating layer, the        method including:    -   a semiconductor-pillar-structure-providing step of providing a        structure including, on a semiconductor substrate, a        semiconductor-pillar base part, the semiconductor pillar being        present on the semiconductor-pillar base part and positioned, in        plan view, within the semiconductor-pillar base part, and an        oxidation-resistant mask material layer surrounding a top        portion and a side surface of the semiconductor pillar; and    -   an oxidation step of using the oxidation-resistant mask material        layer as an oxidation-resistant mask, and oxidizing an entirety        or a bottom portion of the semiconductor-pillar base part and a        surface layer portion of the semiconductor substrate in a region        around the semiconductor-pillar base part, to form an oxide        insulating layer including, in its upper and lower regions,        recessed portions disposed, in plan view, within the        semiconductor pillar,    -   wherein the oxide insulating layer is formed by oxidizing, in        plan view, an entirety of the semiconductor-pillar base part.

Desirably, the semiconductor-pillar-structure-providing step includes

-   -   a first-mask-material-layer formation step of forming a first        mask material layer on the semiconductor substrate,    -   a semiconductor-pillar formation step of etching the        semiconductor substrate through the first mask material layer        serving as an etching mask to form the semiconductor pillar,    -   a second-mask-material-layer formation step of forming a second        mask material layer surrounding a side surface of the        semiconductor pillar, and    -   a semiconductor-pillar-base-part formation step of etching the        semiconductor substrate through the first mask material layer        and the second mask material layer serving as etching masks to        form the semiconductor-pillar base part under the semiconductor        pillar.

Desirably, in the semiconductor-pillar-structure-providing step,

-   -   the first mask material layer and the second mask material layer        are each independently formed as a single layer formed of a        material providing a function of an etching mask and a function        of an oxidation-resistant mask, or each independently formed as        a plurality of layers including, in their outermost portion, the        single layer, and    -   the oxidation-resistant mask material layer is constituted by        the first mask material layer and the second mask material        layer.

Desirably, the semiconductor-pillar-structure-providing step furtherincludes a third-mask-material-layer formation step of forming theoxidation-resistant mask material layer so as to surround thesemiconductor pillar with none of or at least one of the first maskmaterial layer and the second mask material layer disposed between theoxidation-resistant mask material layer and the semiconductor pillar,and so as to surround an upper side surface of the semiconductor-pillarbase part, and

-   -   in the oxidation step, the oxide insulating layer is formed so        as to have an upper end positioned at a level lower than an        upper surface of the semiconductor-pillar base part.

Desirably, the semiconductor-pillar-structure-providing step furtherincludes a step of removing the first mask material layer and/or a stepof removing the second mask material layer.

Desirably, in the third-mask-material-layer formation step, theoxidation-resistant mask material layer is formed so as to surround thesemiconductor pillar with the first mask material layer and the secondmask material layer disposed between the oxidation-resistant maskmaterial layer and the semiconductor pillar, and so as to surround theupper side surface of the semiconductor-pillar base part.

Desirably, in the semiconductor-pillar-base-part formation step, thesecond mask material layer surrounding a bottom side surface of thesemiconductor pillar is formed with a predetermined thickness so as toform the semiconductor-pillar base part having a predetermined width inplan view.

Desirably, in the semiconductor-pillar-structure-providing step,

-   -   a plurality of the semiconductor pillars are formed on and share        the semiconductor-pillar base part, and    -   the oxidation-resistant mask material layer is formed so as to        surround top portions and side surfaces of all the semiconductor        pillars.

Desirably, the semiconductor-pillar-structure-providing step includes

-   -   a first-mask-material-layer formation step of forming a        plurality of first mask material layers on the semiconductor        substrate,    -   a semiconductor-pillar formation step of etching the        semiconductor substrate through the first mask material layers        serving as etching masks to form the plurality of semiconductor        pillars,    -   a second-mask-material-layer formation step of forming a second        mask material layer so as to surround side surfaces of all the        semiconductor pillars, and continuously extend between adjacent        ones of the semiconductor pillars, and    -   a semiconductor-pillar-base-part formation step of etching the        semiconductor substrate through the first mask material layers        and the second mask material layer serving as etching masks, to        form the semiconductor-pillar base part disposed under and        shared by the plurality of semiconductor pillars.

Desirably, the method for producing a pillar-shaped semiconductor devicefurther includes a step of removing a portion of the oxidation-resistantmask material layer, the portion having a band shape having apredetermined width in a height direction, to expose a side surface ofthe semiconductor pillar, and

-   -   a step of using a remaining portion of the oxidation-resistant        mask material layer as an oxidation-resistant mask and oxidizing        the semiconductor pillar from its exposed surface, to form an        additional oxide insulating layer including, in its upper and        lower regions, recessed portions within the semiconductor        pillar.

Desirably, the method for producing a pillar-shaped semiconductor devicefurther includes a step of forming a cover insulating layer so as tocover an exposed surface of the oxide insulating layer,

-   -   a step of providing an exposed side surface of a lower portion        of the semiconductor pillar, and    -   a step of forming a conductor material layer on the cover        insulating layer so as to be in contact with the exposed side        surface of the semiconductor pillar, and formed of alloy or        semiconductor containing a first donor or acceptor impurity.

Desirably, the method for producing a pillar-shaped semiconductor devicefurther includes a step of performing heating to diffuse the first donoror acceptor impurity from the conductor material layer to thesemiconductor pillar, to form the first impurity region in a lowerportion of the semiconductor pillar.

Desirably, the cover insulating layer has a smaller diffusioncoefficient for the first donor or acceptor impurity than the oxideinsulating layer.

Desirably, the method for producing a pillar-shaped semiconductor devicefurther includes a step of, after formation of the cover insulatinglayer, forming the gate insulating layer, the gate conductor layer, anda first material layer in this order so as to cover the semiconductorpillar and the cover insulating layer,

-   -   a step of forming, in a region around a bottom portion of the        semiconductor pillar, an etching material layer containing an        etching material for etching the first material layer, so as to        be in contact with the first material layer,    -   a step of using the etching material to etch the first material        layer that is in contact with the etching material layer,    -   a step of removing the etching material layer,    -   a step of etching the gate conductor layer through a remaining        portion of the first material layer serving as a mask,    -   a step of etching the gate insulating layer through a mask that        is at least one of the first material layer and the gate        conductor layer, to provide an exposed side surface of the        semiconductor pillar, and    -   a step of forming the wiring material layer on the cover        insulating layer so as to be in contact with the exposed side        surface of the semiconductor pillar,    -   wherein the cover insulating layer has an etching block effect        against the etching material.

Desirably, the conductor material layer is a first alloy layercontaining first semiconductor atoms, first metal atoms, and the firstdonor or acceptor impurity,

-   -   the method further includes a step of performing a heat        treatment to form, within the semiconductor pillar, a second        alloy layer that connects to the first alloy layer, that        contains second semiconductor atoms constituting the        semiconductor pillar, the first metal atoms, and the first donor        or acceptor impurity, and that occupies, in plan view, an outer        peripheral portion or an entirety of the semiconductor pillar,        and    -   a step of performing a heat treatment to push out the first        donor or acceptor impurity from the first alloy layer and the        second alloy layer, to form the first impurity region within the        semiconductor pillar.

Desirably, the method for producing a pillar-shaped semiconductor devicefurther includes a step of forming, in a top portion of thesemiconductor pillar, a third impurity region containing a second donoror acceptor impurity,

-   -   a step of depositing second metal atoms having a lower alloying        temperature than the first metal atoms so as to be in contact        with the third impurity region, and    -   a step of performing a heat treatment to form, in a top portion        of the semiconductor pillar, a third alloy layer that contains        the second semiconductor atoms, the second metal atoms, and the        second donor or acceptor impurity, and that occupies, in plan        view, an outer peripheral portion or an entirety of the        semiconductor pillar, and the second impurity region containing        the second donor or acceptor impurity pushed out from the third        alloy layer.

Desirably, the method for producing a pillar-shaped semiconductor devicefurther includes a step of forming a fourth alloy layer that covers atleast a side surface of a top portion of the semiconductor pillar, andthat contains third semiconductor atoms, second metal atoms having alower alloying temperature than the first metal atoms, and a seconddonor or acceptor impurity, and

-   -   a step of performing a heat treatment to form, within the        semiconductor pillar, a third alloy layer that connects to the        fourth alloy layer, that contains the second semiconductor        atoms, the second metal atoms, and the second donor or acceptor        impurity, and that occupies, in plan view, an outer peripheral        portion or an entirety of the semiconductor pillar, and the        second impurity region containing the second donor or acceptor        impurity pushed out from the third alloy layer.

A pillar-shaped semiconductor device according to a second aspect of thepresent invention is

-   -   a pillar-shaped semiconductor device including:    -   an oxide insulating layer being present on a semiconductor        substrate, and including, in upper and lower regions, recessed        portions;    -   a semiconductor pillar that is formed on an upper one of the        recessed portions of the oxide insulating layer, with a        conductor base part disposed between the semiconductor pillar        and the upper one of the recessed portions, the conductor base        part being constituted by a single layer or a plurality of        layers and formed of at least semiconductor, alloy, and metal,        the semiconductor pillar having, in plan view, a smaller width        than the oxide insulating layer;    -   a first impurity region in contact with a lower portion of the        semiconductor pillar;    -   a second impurity region being in contact with the semiconductor        pillar and positioned higher than the first impurity region;    -   a gate insulating layer surrounding a portion of the        semiconductor pillar, the portion being positioned, in a        vertical direction, between the first impurity region and the        second impurity region; and    -   a gate conductor layer surrounding the gate insulating layer,    -   wherein the oxide insulating layer and the conductor base part        constitute a semiconductor-pillar base part on which the        semiconductor pillar stands.

Desirably, the pillar-shaped semiconductor device includes:

-   -   a cover insulating layer covering an upper surface of the oxide        insulating layer; and    -   a wiring material layer connecting to the first impurity region,        formed on the cover insulating layer, and containing a first        donor or acceptor impurity,    -   wherein the cover insulating layer has a smaller diffusion        coefficient for the first donor or acceptor impurity than the        oxide insulating layer.

Desirably, the pillar-shaped semiconductor device further includes:

-   -   a first conductor layer formed on the oxide insulating layer,        containing first semiconductor atoms, first metal atoms, and the        first donor or acceptor impurity, and occupying an outer        peripheral portion or an entirety of the semiconductor pillar;    -   the first impurity region formed on the first conductor layer;        and    -   a second conductor layer formed on the second impurity region,        and containing second semiconductor atoms, second metal atoms        having a lower alloying temperature than the first metal atoms,        and a second donor or acceptor impurity.

Desirably, the pillar-shaped semiconductor device further includes anadditional oxide insulating layer disposed within the semiconductorpillar, positioned higher than the second impurity region, andincluding, in upper and lower regions, recessed portions,

-   -   wherein the semiconductor pillar includes, in a region above the        additional oxide insulating layer, a second pillar-shaped        semiconductor device.

Desirably, the pillar-shaped semiconductor device includes:

-   -   a second oxide insulating layer horizontally connecting to the        oxide insulating layer, and having second recessed portions;    -   a second semiconductor pillar that is formed on an upper one of        the second recessed portions of the second oxide insulating        layer, with a second conductor base part disposed between the        second semiconductor pillar and the upper one of the second        recessed portions, the second conductor base part being        constituted by a single layer or a plurality of layers and        formed of at least semiconductor, alloy, and metal, the second        semiconductor pillar having, in plan view, a smaller width than        the second oxide insulating layer and the second conductor base        part;    -   a third impurity region in contact with a lower portion of the        second semiconductor pillar;    -   a fourth impurity region being in contact with the second        semiconductor pillar and positioned higher than the third        impurity region;    -   a second gate insulating layer surrounding a portion of the        second semiconductor pillar, the portion being positioned, in a        vertical direction, between the third impurity region and the        fourth impurity region; and    -   a second gate conductor layer surrounding the second gate        insulating layer,    -   wherein the second oxide insulating layer and the second        conductor base part constitute a second semiconductor-pillar        base part on which the second semiconductor pillar stands.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1AA to 1AC are a plan view and sectional structural views thatillustrate a method for producing an SGT-including pillar-shapedsemiconductor device according to a first embodiment of the presentinvention.

FIGS. 1BA to 1BC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the first embodiment.

FIGS. 1CA to 1CC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the first embodiment.

FIGS. 1DA to 1DC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the first embodiment.

FIGS. 1EA to 1EC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the first embodiment.

FIGS. 1FA to 1FC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the first embodiment.

FIGS. 1GA to 1GC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the first embodiment.

FIGS. 1HA to 1HC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the first embodiment.

FIGS. 1IA to 1IC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the first embodiment.

FIGS. 1JA to 1JC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the first embodiment.

FIGS. 1KA to 1KC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the first embodiment.

FIGS. 2AA to 2AC are a plan view and sectional structural views thatillustrate a method for producing an SGT-including pillar-shapedsemiconductor device according to a second embodiment of the presentinvention.

FIGS. 2BA to 2BC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the second embodiment.

FIGS. 2CA to 2CC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the second embodiment.

FIGS. 2DA to 2DC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the second embodiment.

FIGS. 2EA to 2EC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the second embodiment.

FIGS. 2FA to 2FC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the second embodiment.

FIGS. 3AA to 3AC are a plan view and sectional structural views thatillustrate a method for producing an SGT-including pillar-shapedsemiconductor device according to a third embodiment of the presentinvention.

FIGS. 3BA to 3BC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the third embodiment.

FIGS. 3CA to 3CC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the third embodiment.

FIGS. 3DA to 3DC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the third embodiment.

FIGS. 3EA to 3EC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the third embodiment.

FIGS. 4AA to 4AC are a plan view and sectional structural views thatillustrate a method for producing an SGT-including pillar-shapedsemiconductor device according to a fourth embodiment of the presentinvention.

FIGS. 4BA to 4BC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the fourth embodiment.

FIGS. 4CA to 4CC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the fourth embodiment.

FIGS. 4DA to 4DC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the fourth embodiment.

FIGS. 4EA to 4EC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the fourth embodiment.

FIGS. 5AA to 5AC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to a fifth embodiment of the presentinvention.

FIGS. 5BA to 5BC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the fifth embodiment.

FIGS. 5CA to 5CC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the fifth embodiment.

FIGS. 5DA to 5DC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the fifth embodiment.

FIGS. 5EA to 5EC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the fifth embodiment.

FIGS. 6AA to 6AC are a plan view and sectional structural views thatillustrate a method for producing an SGT-including pillar-shapedsemiconductor device according to a sixth embodiment of the presentinvention.

FIGS. 6BA to 6BC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the sixth embodiment.

FIGS. 6CA to 6CC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the sixth embodiment.

FIGS. 7AA to 7AC are a plan view and sectional structural views thatillustrate a method for producing an SGT-including pillar-shapedsemiconductor device according to a seventh embodiment of the presentinvention.

FIGS. 7BA to 7BC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the seventh embodiment.

FIGS. 8AA to 8AC are a plan view and sectional structural views thatillustrate a method for producing an SGT-including pillar-shapedsemiconductor device according to an eighth embodiment of the presentinvention.

FIGS. 8BA to 8BC are a plan view and sectional structural views thatillustrate the method for producing an SGT-including pillar-shapedsemiconductor device according to the eighth embodiment.

FIG. 9 is a schematic structural view of an existing SGT.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, methods for producing a pillar-shaped semiconductor deviceaccording to embodiments of the present invention will be described withreference to the drawings.

First Embodiment

Hereinafter, with reference to FIG. 1AA to FIG. 1KC, a method forproducing an SGT-including pillar-shaped semiconductor device accordingto a first embodiment of the present invention will be described. AmongFIG. 1AA to FIG. 1KC, figures suffixed with A are plan views; figuressuffixed with B are sectional structural views taken along lines X-X′ inthe corresponding figures suffixed with A; and figures suffixed with Care sectional structural views taken along lines Y-Y′ in thecorresponding figures suffixed with A.

As illustrated in FIGS. 1AA to 1AC, on a Si substrate 1, a siliconnitride (Si₃N₄) layer and a SiO₂ layer that have a circular shape inplan view are stacked in this order, to thereby form a mask materiallayer 2 constituted by these two layers.

Subsequently, as illustrated in FIGS. 1BA to 1BC, the Si substrate 1 isetched through the mask material layer 2 serving as a mask by an RIE(Reactive Ion Etching) process, to form a Si pillar 3 on a Si substrate1 a.

Subsequently, as illustrated in FIGS. 1CA to 1CC, an ALD (Atomic LayerDeposition) process is performed over the whole structure to stack aSiO₂ layer, a silicon nitride (Si₃N₄) layer, and a SiO₂ layer (notshown) in this order so as to cover the surfaces of the Si pillar 3 andthe Si substrate 1 a. Subsequently, an RIE process is performed to etchthese three layers so as to leave a mask material layer 4 disposedaround the side surface of the Si pillar 3 and constituted by the SiO₂layer, the Si₃N₄ layer, and the SiO₂ layer.

Subsequently, as illustrated in FIGS. 1DA to 1DC, an RIE process isperformed to etch the Si substrate 1a through the mask material layers 2and 4, to form a Si-pillar base part 5 under the Si pillar 3. In thiscase, the Si-pillar base part 5 is formed so as to surround the Sipillar 3 in plan view.

Subsequently, as illustrated in FIGS. 1EA to 1EC, the mask materiallayers 2 and 4 are used as masks to selectively oxidize portions formedof Si from their exposed surfaces, to thereby form a SiO₂ layer 10,which is a combination of a portion of the lower portion of the Sipillar 3, the whole Si-pillar base part 5, and the surface of the Sisubstrate 1 a. The central portion of the lower portion of the Si pillar3 is far from the exposed surfaces and is less likely to be oxidized; asa result, a recessed portion 10 a is formed in the top portion of theSiO₂ layer 10 (the top portion serving as the interface between the SiO₂layer 10 and the Si pillar 3) so as to be recessed toward the center. Inaddition, a portion (immediately below the Si pillar 3) of the Sisubstrate 1 a is also far from the exposed surfaces and is less likelyto be oxidized; as a result, a recessed portion 10 b is formed in thebottom portion of the SiO₂ layer 10 (the bottom portion serving as theinterface between the SiO₂ layer 10 and the Si substrate 1 a) so as tobe recessed toward the center.

Subsequently, as illustrated in FIGS. 1FA to 1FC, the mask materiallayer 4 is removed. Subsequently, a Si₃N₄ layer 12 is formed on the SiO₂layer 10 that is positioned in a region around the Si pillar 3, so as tohave an upper surface positioned at a level at or near the top portionof the SiO₂ layer 10. Subsequently, an ALD process is performed over thewhole structure to stack a hafnium oxide (HfO₂) layer 13, a titaniumnitride (TiN) layer 14, and a SiO₂ layer 15 in this order. Subsequently,a resist layer 16 is formed on the SiO₂ layer 15 that is positioned in aregion around the Si pillar 3.

Subsequently, in the step illustrated in FIGS. 1GA to 1GC, hydrogenfluoride gas (hereafter, referred to as “HF gas”) is fed to the wholestructure. Subsequently, the ambient temperature is increased to, forexample, 180° C., so that the HF gas is ionized by water containedwithin the resist layer 16, to generate hydrogen fluoride ions (HF₂ ⁺)(hereafter, referred to as “HF ions”). The HF ions diffuse through theresist layer 16 to etch the SiO₂ layer 15 that is in contact with theresist layer 16 (for the mechanism of this etching, refer to TadashiShibata, Susumu Kohyama and Hisakazu lizuka: “A New Field IsolationTechnology for High Density MOS LSI”, Japanese Journal of AppliedPhysics, Vol. 18, pp. 263-267 (1979)). On the other hand, the SiO₂ layer15 that is not in contact with the resist layer 16 is substantially notetched and is left as a SiO₂ layer 15 a. Subsequently, the resist layer16 is removed. Furthermore, the SiO₂ layer 15 a is used as a mask toetch the titanium nitride (TiN) layer 14, to thereby form a TiN layer 14a. Subsequently, at least one of the SiO₂ layer 15 a and the TiN layer14 a is used as a mask to etch the HfO₂ layer 13, to thereby form a HfO₂layer 13 a. An etchant appropriately selected enables etching of one orboth of the SiO₂ layer 15 a and the TiN layer 14 a. Subsequently, theexposed surface layer of the TiN layer 14 a is oxidized to form atitanium oxide (TiO) layer 17. In this way, the structure illustrated inFIGS. 1GA to 1GC is provided.

Subsequently, as illustrated in FIGS. 1HA to 1HC, a nickel silicide(NiSi) layer 19 containing, for example, a donor impurity is formed onthe Si₃N₄ layer 12 so as to surround the Si pillar 3. Subsequently, aheat treatment is performed to diffuse the donor impurity from the NiSilayer 19 into the Si pillar 3, to thereby form an N⁺ layer 20.Alternatively, the NiSi layer 19 may be replaced by a semiconductorlayer containing a donor impurity, such as a Si layer.

Subsequently, as illustrated in FIGS. 1IA to 1IC, a Si₃N₄ layer 21 isformed so as to cover the Si₃N₄ layer 12 and the NiSi layer 19 and havean upper surface positioned at an intermediate level in the heightdirection of the Si pillar 3. Subsequently, an intermediate portion ofthe SiO₂ layer 15 a is etched, and then a NiSi layer 22 connecting tothe TiN layer 14 a is formed on the Si₃N₄ layer 21.

Subsequently, as illustrated in FIGS. 1JA to 1JC, a SiO₂ layer 24 isformed so as to have an upper surface positioned at a level below thetop portion of the Si pillar 3. Subsequently, the SiO₂ layer 24 is usedas a mask to remove, from the top portion of the Si pillar, the SiO₂layer 15 a, the TiN layer 14 a, and the HfO₂ layer 13 a. Subsequently,an N⁺ layer 25 is formed by ion implantation, for example.

Subsequently, as illustrated in FIGS. 1KA to 1KC, a SiO₂ layer 27 isformed over the whole structure. Subsequently, a contact hole 28 a isformed to the NiSi layer 19. Similarly, a contact hole 28 b is formed tothe N⁺ layer 25. Similarly, a contact hole 28 c is formed to the NiSilayer 22. Subsequently, a wiring metal layer MS is formed on the SiO₂layer 27 so as to connect through the contact hole 28 a to the NiSilayer 19. Similarly, a wiring metal layer MD is formed on the SiO₂ layer27 so as to connect through the contact hole 28 b to the N⁺ layer 25.Similarly, a wiring metal layer MG is formed on the SiO₂ layer 27 so asto connect through the contact hole 28 c to the NiSi layer 22. Thus, anSGT has been formed on the Si substrate 1 a.

The production method according to the first embodiment provides thefollowing advantages.

1. The first mask material layer 2 and the second mask material layer 4each have both of a function of an etching mask during etching of the Sisubstrate 1 a, and a function of an oxidation-resistant mask duringformation of the SiO₂ layer 10 by oxidation. This enables simplificationof the steps, which leads to a reduction in the costs.

2. The Si-pillar base part 5, which is formed with the first maskmaterial layer 2 and the second mask material layer 4 serving as etchingmasks, surrounds the side surface of the Si pillar 3 in plan view. Inother words, the Si-pillar base part 5 is formed by self-alignmentwithout the necessity of performing a mask alignment step in alithographic process. Thus, a high-density SGT-including circuit isformed at low costs.

3. The SiO₂ layer 10, which supports the Si pillar 3 in which the SGT isformed, is wider than the Si pillar 3 in plan view, so that the Sipillar 3 resists external stress and is less likely to collapse. Becauseof the difference between the stress coefficients of SiO₂ and Si, theinterface between the Si pillar 3 and the SiO₂ layer 10 is relativelyweak; when a step such as a washing step applies a force to the Sipillar 3, the Si pillar 3 may separate from the SiO₂ layer 10 andcollapse; however, this is prevented by the recessed portion 10 a formedat the interface between the Si pillar 3 and the SiO₂ layer 10.Similarly, the recessed portion 10 b prevents the SiO₂ layer 10 fromseparating from the Si substrate 1 aand collapsing. This is particularlyadvantageous when the SiO₂ layer 10 is formed so as to have a largeheight in order to enhance the effect of insulation between the Sisubstrate 1 a and the SGT. The narrower the Si pillar 3 and the SiO₂layer 10 (in particular, a portion derived from the Si-pillar base part5) are formed in order to increase the density of the circuit, the moreimportant the above-described three stabilization effects become.

4. As illustrated in FIGS. 1KA to 1KC, the SiO₂ layer 10 is formed so asto connect to the whole bottom portion of the Si pillar 3 and thesurface layer of the Si substrate 1 a. As a result, the SGT formed inthe Si pillar 3 is insulated by the SiO₂ layer 10 from the Si substrate1 a. This means that using not an SOI substrate but the Si substrate 1astill provides the advantages due to use of an SOI substrate. In otherwords, the necessity of forming a P well and an N well has beeneliminated, which have been formed in the case of forming anSGT-including CMOS circuit with a Si substrate. Thus, the necessity ofusing expensive SOI wafers and the necessity of forming P wells and Nwells have been eliminated, which enables a considerable reduction inthe production costs.

Second Embodiment

Hereinafter, with reference to FIG. 2AA to FIG. 2FC, a method forproducing an SGT-including pillar-shaped semiconductor device accordingto a second embodiment of the present invention will be described. AmongFIG. 2AA to FIG. 2FC, figures suffixed with A are plan views; figuressuffixed with B are sectional structural views taken along lines X-X′ inthe corresponding figures suffixed with A; and figures suffixed with Care sectional structural views taken along lines Y-Y′ in thecorresponding figures suffixed with A. The production method accordingto the second embodiment is the same as in the steps according to thefirst embodiment illustrated in FIG. 1AA to FIG. 1KC except for thefollowing differences.

As illustrated in FIGS. 2AA to 2AC, a mask material layer 2 is used as amask to etch a Si substrate 1 b by an RIE process, to form a Si pillar 3a on the Si substrate 1 b. Incidentally, the mask material layer 2 maybe formed of a material not providing the function of anoxidation-resistant mask as long as it functions as an etching mask.

Subsequently, as illustrated in FIGS. 2BA to 2BC, as with the maskmaterial layer 4 according to the first embodiment, a mask materiallayer 30 is formed so as to surround the outer circumferential sidesurface of the Si pillar 3 a. Incidentally, the mask material layer 30may be formed of a material not providing the function of anoxidation-resistant mask as long as it functions as an etching mask.

Subsequently, as illustrated in FIGS. 2CA to 2CC, an RIE process isperformed through the mask material layers 2 and 30 serving as masks toetch the Si substrate 1 b, to thereby form a Si-pillar base part 31under the Si pillar 3 a so as to surround the Si pillar 3 a in planview. Subsequently, the mask material layer 30 is removed; an ALDprocess is then performed over the whole structure to stack a SiO₂ layer32, a Si₃N₄ layer 33, and a SiO₂ layer 34 in this order. Subsequently, aresist layer 35 is formed in a region around the Si-pillar base part 31so as to have an upper surface positioned lower than the upper surfaceof the Si-pillar base part 31.

Subsequently, as illustrated in FIGS. 2DA to 2DC, the same process as inFIGS. 1GA to 1GC is performed to etch portions (adjacent to the resistlayer 35) of the SiO₂ layer 32, the Si₃N₄ layer 33, and the SiO₂ layer34. Subsequently, the resist layer 35 is removed. This provides a SiO₂layer 32 a, a Si₃N₄ layer 33 a, and a SiO₂ layer 34 a, which cover theupper portion of the Si-pillar base part 31 and the Si pillar 3 a.

Subsequently, as illustrated in FIGS. 2EA to 2EC, wet oxidation isperformed to oxidize the surface layer of the Si substrate 1 b and thebottom portion of the Si-pillar base part 31, which are not covered bythe Si₃N₄ layer 33 a, to thereby form a SiO₂ layer 36. The SiO₂ layer 36is formed through the Si₃N₄ layer 33 a serving as a mask, so that thecentral portion is less likely to be oxidized. As a result, recessedportions 36 a and 36 b are formed in upper and lower regions of theSi-pillar base part 31. Subsequently, the SiO₂ layer 32 a, the Si₃N₄layer 33 a, and the SiO₂ layer 34 a are removed.

Subsequently, the same steps as in FIG. 1FA to FIG. 1KC are performed tothereby form, as illustrated in FIGS. 2FA to 2FC, an SGT on the Sisubstrate 1 b. In the top portion of the remaining Si-pillar base part31, an impurity region serving as the source or drain of the SGT andcontaining donor impurity atoms may be formed so as to be in contactwith the Si pillar 3 a. In this case, formation of the NiSi layer 19 andthe N⁺ layer 20 is no longer necessary. The contact hole 28a is formedso as to extend to the impurity region in the top portion of theremaining Si-pillar base part 31. On or within the top portion of theremaining Si-pillar base part 31, a single semiconductor layer or aplurality of semiconductor layers containing metal, alloy, or donor oracceptor impurity atoms may be formed.

The production method according to the second embodiment provides thefollowing advantages.

1. In this embodiment, the SiO₂ layer 36 having, in its upper and lowerregions, the recessed portions 36 a and 36 b is formed in the Si-pillarbase part 31, which is wider than the Si pillar 3 a. The interfacebetween the Si pillar 3 a and the SiO₂ layer 36 is positioned within thewide Si-pillar base part 31. As a result, in subsequent steps, the Sipillar 3 a is even less likely to collapse.

2. The SiO₂ layer 36 is formed so as to connect to the whole bottomportion of the Si-pillar base part 31 and the surface layer of the Sisubstrate 1 b. As a result, the SGT formed in the Si pillar 3 a isinsulated by the SiO₂ layer 36 from the Si substrate 1 b. This means, asin the first embodiment, elimination of the necessity of use of SOIsubstrates and elimination of the necessity of formation of P wells andN wells during formation of SGT-including CMOS circuits. This enables aconsiderable reduction in the production costs.

3. In the first embodiment, the mask material layers 2 and 4 have bothof a function of an etching mask and a function of anoxidation-resistant mask. By contrast, in this embodiment, the maskmaterial layers 2 and 30 may be formed to have the function of anetching mask alone. This increases the degree of freedom of selectingmaterials for the mask material layers 2 and 30 and theoxidation-resistant mask (in this embodiment, the SiO₂ layer 32 a, theSi₃N₄ layer 33 a, and the SiO₂ layer 34 a).

Third Embodiment

Hereinafter, with reference to FIG. 3AA to FIG. 3EC, a method forproducing an SGT-including pillar-shaped semiconductor device accordingto a third embodiment of the present invention will be described. AmongFIG. 3AA to FIG. 3EC, figures suffixed with A are plan views; figuressuffixed with B are sectional structural views taken along lines X-X′ inthe corresponding figures suffixed with A; and figures suffixed with Care sectional structural views taken along lines Y-Y′ in thecorresponding figures suffixed with A. The production method accordingto the third embodiment is the same as in the steps according to thefirst embodiment illustrated in FIG. 1AA to FIG. 1KC except for thefollowing differences.

As illustrated in FIGS. 3AA to 3AC, on a Si substrate 1 (not shown), aSi₃N₄ layer 2 a and a SiO₂ layer 2 b that have a circular shape in planview are stacked in this order. The Si₃N₄ layer 2 a and the SiO₂ layer 2b are used as masks to etch the Si substrate 1 by an RIE process, tothereby form a Si pillar 3 a on the Si substrate 1 b. Subsequently, anALD process is performed over the whole structure to stack a SiO₂ layer,a Si₃N₄ layer, and a SiO₂ layer (not shown) in this order so as to coverthe surfaces of the Si pillar 3 a and the Si substrate 1 b.Subsequently, an RIE process is performed to etch these three layers soas to leave a mask material layer 30 a constituted by the SiO₂ layer,the silicon nitride (Si₃N₄) layer, and the SiO₂ layer that surround theside surface of the Si pillar 3 a.

Subsequently, as illustrated in FIGS. 3BA to 3BC, an RIE process isperformed to etch the Si substrate 1 b through the SiO₂ layer 2 b andthe mask material layer 30 a serving as masks, to thereby form aSi-pillar base part 31 a under the Si pillar 3 a. In this case, theSi-pillar base part 31 a is formed so as to surround the Si pillar 3 ain plan view. In the etching by an RIE process, the width Ls of thebottom portion of the mask material layer 30 a surrounding the Si pillar3 a in plan view can be changed by changing the height Lh of the SiO₂layer 2 b. In this way, the Si-pillar base part 31 a can be formed so asto have a desired diameter Ld. Alternatively, the Si-pillar base part 31a can also be formed so as to have a desired diameter Ld by changing thethickness of the mask material layer 30 a deposited to change thethickness Ls of the bottom portion of the mask material layer 30 a.

Subsequently, as illustrated in FIGS. 3CA to 3CC, the Si₃N₄ layer 2 aand the mask material layer 30 a are used as masks to selectivelyoxidize portions formed of Si from their exposed surfaces, to therebyform a SiO₂ layer 37, which is a combination of a portion of the lowerportion of the Si pillar 3 a, the whole Si-pillar base part 31 a, andthe surface of the Si substrate 1 b. The central portion of the lowerportion of the Si pillar 3 a is far from the exposed surfaces and isless likely to be oxidized; as a result, a recessed portion 37 a isformed in the top portion of the SiO₂ layer 37 (the top portion servingas the interface between the SiO₂ layer 37 and the Si pillar 3 a) so asto be recessed toward the center. A portion (immediately below the Sipillar 3 a) of the Si substrate 1 b is also far from the exposedsurfaces and less likely to be oxidized; as a result, a recessed portion37 b is formed in the bottom portion of the SiO₂ layer 37 (the bottomportion serving as the interface between the SiO₂ layer 37 and the Sisubstrate 1 b) so as to be recessed toward the center.

Subsequently, as illustrated in FIGS. 3DA to 3DC, an ALD process isperformed to deposit a Si₃N₄ layer (not shown) over the whole structure.Subsequently, a SiO₂ layer (not shown) is deposited over the wholestructure. Subsequently, a CMP (Chemical Mechanical Polishing) processis performed to polish the structure down to the level of the uppersurface of the Si₃N₄ layer 2 a, to thereby form a Si₃N₄ layer 39 and aSiO₂ layer 40.

Subsequently, as illustrated in FIGS. 3EA to 3EC, the SiO₂ layer 40, theSi₃N₄ layers 2 a and 39, and the mask material layer 30 a are removed.Subsequently, the steps as in FIG. 1FA to FIG. 1KC are performed. Thisforms an SGT disposed on the Si substrate 1 b and isolated from the Sisubstrate 1 b by the SiO₂ layer 37.

The production method according to the third embodiment provides thefollowing advantages: as illustrated in FIGS. 3BA to 3BC, by changingthe height Lh of the SiO₂ layer 2 b or by changing the thickness of themask material layer 30 a deposited, the Si-pillar base part 31 a isformed so as to have a desired diameter Ld.

Fourth Embodiment

Hereinafter, with reference to FIG. 4AA to FIG. 4EC, a method forproducing an SGT-including pillar-shaped semiconductor device accordingto a fourth embodiment of the present invention will be described. Inthis embodiment, two SGTs are formed on a single elongated Si-pillarbase part, to produce a CMOS inverter circuit. Among FIG. 4AA to FIG.4EC, figures suffixed with A are plan views; figures suffixed with B aresectional structural views taken along lines X-X′ in the correspondingfigures suffixed with A; and figures suffixed with C are sectionalstructural views taken along lines Y-Y′ in the corresponding figuressuffixed with A. The production method according to the fourthembodiment is the same as in the steps according to the first embodimentillustrated in FIG. 1AA to FIG. 1KC except for the followingdifferences.

As illustrated in FIGS. 4AA to 4AC, on a Si substrate 1 (not shown), aSi₃N₄ layer 2 aa and a SiO₂ layer 2 ab are stacked in this order; on theSi substrate 1, a Si₃N₄ layer 2 ba and a SiO₂ layer 2 bb are stacked inthis order; an RIE process is performed through these combinations oflayers serving as masks, to form Si pillars 3 aa and 3 ab, which standadjacent to each other. Subsequently, an ALD process is performed overthe whole structure to stack a SiO₂ layer, a Si₃N₄ layer, and a SiO₂layer (not shown) in this order so as to cover the surfaces of the Sipillars 3 aa and 3 ab and a Si substrate 1 c. Subsequently, an RIEprocess is used to etch these three layers so as to leave a maskmaterial layer 30 b, which surrounds the side surfaces of the Si pillars3 aa and 3 ab, also continuously extends between the Si pillars 3 aa and3 ab, and is constituted by the SiO₂ layer, the Si₃N₄ layer, and theSiO₂ layer. The portion (continuously extending between the Si pillars 3aa and 3 ab) of the mask material layer 30 b can be formed by, forexample, appropriately adjusting the height of the SiO₂ layers 2 ab and2 bb or the distance between the Si pillars 3 aa and 3 ab.

Subsequently, as illustrated in FIGS. 4BA to 4BC, the SiO₂ layers 2 aband 2 bb and the mask material layer 30 b are used as masks and an RIEprocess is performed to etch the Si substrate 1 c, to form a Si-pillarbase part 41.

Subsequently, as illustrated in FIGS. 4CA to 4CC, selective oxidation isperformed through the Si₃N₄ layers 2 aa and 2 ba and the mask materiallayer 30 b serving as masks, to form a SiO₂ layer 42, which is acombination of portions of the lower portions of the Si pillars 3 ba and3 bb, the whole Si-pillar base part 41, and the surface of the Sisubstrate 1 c. As with the recessed portions 10 a and 10 b in the firstembodiment, as illustrated in FIG. 4CC, recessed portions 42 a and 42 bare formed in the upper and lower regions of the SiO₂ layer 42. Therecessed portion 42 b has a width along line X-X′, the width beinglarger than that of the recessed portion 10 b.

Subsequently, as illustrated in FIGS. 4DA to 4DC, the SiO₂ layers 2 aband 2 bb, the Si₃N₄ layers 2 aa, 2 ba, and 39, and the mask materiallayer 30 b are removed.

Subsequently, as illustrated in FIGS. 4EA to 4EC, the same steps as inFIG. 1FA to 1KC are performed, to form a CMOS inverter circuit in whichthe Si substrate 1 c and the two SGTs are isolated by the SiO₂ layer 42.The Si₃N₄ layer 45 is formed in regions around the Si pillars 3 ba and 3bb so as to have an upper surface positioned at the same level as thelevel of the upper surface of the SiO₂ layer 42. Subsequently, the samesteps as in FIG. 1GA to FIG. 1HC are performed, to form gate insulatingHfO₂ layers 46 a and 46 b, gate conductor TiN layers 47 a and 47 b, andSiO₂ layers 48 a and 48 b so as to surround the Si pillars 3 ba and 3bb. Subsequently, Si surfaces of the bottom portions of the Si pillars 3ba and 3 bb are exposed. Subsequently, a wiring NiSi layer 50 a and awiring NiSi layer 50 b are formed: the wiring NiSi layer 50 a contains,for example, an acceptor impurity and is in contact with the Si surfacesof the bottom portions of the Si pillars 3 ba and 3 bb; and the wiringNiSi layer 50 b connects to the wiring NiSi layer 50 a and contains adonor impurity. Subsequently, a heat treatment is performed, to form aP⁺ layer 43 a in the bottom portion of the Si pillar 3 ba, and an N⁺layer 43 b in the bottom portion of the Si pillar 3 bb. Subsequently, aSi₃N₄ layer 51 is formed so as to have an upper surface (in the heightdirection) positioned at a level corresponding to an intermediateportion of the gate conductor TiN layer 47 a, and surround the Sipillars 3 ba and 3 bb. Subsequently, portions of the SiO₂ layers 48 aand 48 b are etched off, and then a wiring NiSi layer 52 is formed onthe Si₃N₄ layer 51 so as to be in contact with the outer circumferencesof the gate conductor TiN layers 47 a and 47 b. Subsequently, a SiO₂layer 53 is formed so as to have an upper surface (in the heightdirection) positioned lower than the top portions of the gate conductorTiN layers 47 a and 47 b. Subsequently, a P⁺ layer 54 a and an N⁺ layer54 b are formed in the top portions of the Si pillars 3 ba and 3 bb byion implantation, for example. Subsequently, a SiO₂ layer 56 is formedover the whole structure. Subsequently, a contact hole 57 a is formed soas to extend from the upper surface of the SiO₂ layer 56 to the wiringNiSi layer 50 a; a contact hole 57 b is formed so as to extend from theupper surface of the SiO₂ layer 56 to the P⁺ layer 54 a; a contact hole57 c is formed so as to extend from the upper surface of the SiO₂ layer56 to the wiring NiSi layer 52; and a contact hole 57 d is formed so asto extend from the upper surface of the SiO₂ layer 56 to the N⁺ layer 54b. Subsequently, an output wiring metal layer Vout is formed so as toconnect through the contact hole 57 a to the wiring NiSi layer 50; apower supply wiring metal layer Vdd is formed so as to connect throughthe contact hole 57 b to the P⁺ layer 54 a; an input wiring metal layerVin is formed so as to connect through the contact hole 57 c to thewiring NiSi layer 52; and a ground wiring metal layer Vss is formed soas to connect through the contact hole 57 d to the N⁺ layer 54 b.

The production method according to the fourth embodiment provides thefollowing advantages.

1. In this embodiment, since the Si-pillar base part 41 is widely formedso as to continuously extend under the two Si pillars 3 ba and 3 bb, theSi pillars 3 ba and 3 bb resists an external stress in the X-X′direction, and are less likely to collapse. The Si pillars 3 ba and 3 bband the SiO₂ layer 42 also resist another external stress in the Y-Y′direction, and are less likely to collapse because of, as in the firstembodiment, the presence of the recessed portions 42 a and 42 b in theupper and lower regions of the SiO₂ layer 42.

2. The SiO₂ layer 42 is formed so as to extend through the whole bottomportion of the Si-pillar base part 41 to the surface layer of the Sisubstrate 1 c. As a result, the SGTs formed in the Si pillars 3 ba and 3bb are insulated by the SiO₂ layer 42 from the Si substrate 1 c. Thismeans, as in the first embodiment, elimination of the necessity of useof SOI substrates and elimination of the necessity of formation of Pwells and N wells during formation of SGT-including CMOS circuits. Thisenables a considerable reduction in the production costs.

Fifth Embodiment

Hereinafter, with reference to FIG. 5AA to FIG. 5EC, a method forproducing a CMOS inverter circuit including a double-stacked SGTaccording to a fifth embodiment of the present invention will bedescribed. Among FIG. 5AA to FIG. 5EC, figures suffixed with A are planviews; figures suffixed with B are sectional structural views takenalong lines X-X′ in the corresponding figures suffixed with A; andfigures suffixed with C are sectional structural views taken along linesY-Y′ in the corresponding figures suffixed with A. The production methodaccording to the fifth embodiment is the same as in the steps accordingto the first embodiment illustrated in FIG. 1AA to FIG. 1KC except forthe following differences.

As illustrated in FIGS. 5AA to 5AC, a mask material layer 2 c (formed aswith the mask material layer 2 of the first embodiment) is used as amask and an RIE process is performed to form a Si pillar 3 c; an ALDprocess is performed to form a SiO₂ layer (not shown), a Si₃N₄ layer(not shown), and a SiO₂ layer (not shown) so as to cover the entirety ofthe Si pillar 3 c and a Si substrate 1 e. Subsequently, the SiO₂ layer,the Si₃N₄ layer, and the SiO₂ layer are removed so as to expose the Sisurfaces of the bottom portion of the Si pillar 3 c and the uppersurface of the Si substrate 1 e, to thereby form a SiO₂ layer 73, aSi₃N₄ layer 74, and a SiO₂ layer 75. Subsequently, the SiO₂ layer 73,the Si₃N₄ layer 74, and the SiO₂ layer 75 are used as masks and thebottom portion of the Si pillar 3 c and the adjoining upper surface ofthe Si substrate 1 e are selectively oxidized to form a SiO₂ layer 72.As a result, recessed portions 72 a and 72 b are formed in the upper andlower regions of the SiO₂ layer 72 under the Si pillar 3 c.

Subsequently, as illustrated in FIGS. 5BA to 5BC, a Si₃N₄ layer 76 isformed in a region around the Si pillar 3 c. Subsequently, the SiO₂layer 73, the Si₃N₄ layer 74, and the SiO₂ layer 75 are removed so as toexpose the Si surface of the bottom portion of the Si pillar 3 c abovethe SiO₂ layer 72, to form a SiO₂ layer 73 a, a Si₃N₄ layer 74 a, and aSiO₂ layer 75 a. Subsequently, a WSi layer 77 is formed so as to be incontact with the exposed Si surface of the Si pillar 3 c, surround theSi pillar 3 c, extend in a horizontal direction, and contain a donorimpurity. Subsequently, a heat treatment is performed to diffuse thedonor impurity within the WSi layer into the Si pillar 3 c, to form anN⁺ layer 78.

Subsequently, as illustrated in FIGS. 5CA to 5CC, a SiO₂ layer 80 isformed in a region around the Si pillar 3 c so as to have an uppersurface positioned higher than the upper surface of the WSi layer 77.Subsequently, a Si₃N₄ layer 81 is formed in a region around the Sipillar 3 c so as to have an upper surface positioned at a levelcorresponding to an intermediate portion of the Si pillar 3 c.Subsequently, a resist layer (not shown) is formed; as in FIGS. 1GA to1GC, the HF ion diffusion process using the resist layer is performed,to expose the Si surface of a portion of the circumferential portion ofthe Si pillar 3 c. As a result, the SiO₂ layer 73 a, the Si₃N₄ layer 74a, and the SiO₂ layer 75 a are divided to form, in the lower portion, aSiO₂ layer 73 b, a Si₃N₄ layer 74 b, and a SiO₂ layer 75 b, and to form,in the upper portion, a SiO₂ layer 73 c, a Si₃N₄ layer 74 c, and a SiO₂layer 75 c. Subsequently, the SiO₂ layers 73 a and 73 b, the Si₃N₄layers 74 a, 74 b, and 81, and the SiO₂ layers 75 a and 75 b are used asmasks and the portion (having the exposed Si surface) of the Si pillar 3c is selectively oxidized to the central portion in plan view, to form aSiO₂ layer 82. This selective oxidation forms recessed portions 82 a and82 b, which are disposed in the upper and lower regions of the SiO₂layer 82 and are recessed toward the center. Subsequently, from theregion around the Si pillar 3 c, the Si₃N₄ layer 81, the SiO₂ layers 73a and 73 b, the Si₃N₄ layers 74 a and 74 b, and the SiO₂ layers 75 a and75 b are removed.

Subsequently, as illustrated in FIGS. 5DA to 5DC, a HfO₂ layer (notshown), a TiN layer (not shown), and a SiO₂ layer (not shown) are formedso as to cover the whole Si pillar 3 c, to connect to the Si pillar 3 c,and to extend to the SiO₂ layer 80. Subsequently, a Si₃N₄ layer 87 isformed in a region around the Si pillar 3 c so as to have an uppersurface positioned at a level below the SiO₂ layer 82. Subsequently,portions of the HfO₂ layer, the TiN layer, and the SiO₂ layersandwiching the SiO₂ layer 82 are etched off to expose the Si surface ofthe Si pillar 3 c in the height direction. This etching forms, for thelower portion of the Si pillar 3 c, a HfO₂ layer 83 a, a TiN layer 84 a,and a SiO₂ layer 85 a, and, for the upper portion of the Si pillar 3 c,a HfO₂ layer 83 b, a TiN layer 84 b, and a SiO₂ layer 85 b.Subsequently, the exposed surfaces of the TiN layers 84 a and 84 b areoxidized to form TiO layers 89 a and 89 b. Subsequently, on the Si₃N₄layer 87 disposed in a region around the Si pillar 3 c, a NiSi layer 92,a SiO₂ layer 93, and a NiSi layer 94 are stacked upward in this order:the NiSi layer 92 is in contact with the exposed Si surface of the Sipillar 3 c and contains a donor impurity; the SiO₂ layer 93 is incontact with the SiO₂ layer 82; and the NiSi layer 94 is in contact withthe exposed Si surface of the Si pillar 3 c and contains an acceptorimpurity. Subsequently, a heat treatment is performed to diffuse thedonor and acceptor impurities from the NiSi layers 92 and 94 into the Sipillar 3 c, to form an N⁺ layer 96 and a P⁺ layer 97 within the Sipillar 3 c.

Subsequently, as illustrated in FIGS. 5EA to 5EC, a Si₃N₄ layer 98 isformed in a region around the Si pillar 3 c so as to have an uppersurface positioned (in the height direction) at a level corresponding toan intermediate portion of the TiN layer 84 b. Subsequently, on theSi₃N₄ layer 98, a NiSi layer 100 is formed so as to be in contact withthe TiN layer 84 b. Subsequently, in the region around the Si pillar 3c, a SiO₂ layer 101 is formed so as to have an upper surface positioned(in the height direction) at a level lower than the top portion of theSi pillar 3 c. Subsequently, the HfO₂ layer 83 b, the TiN layer 84 b,the SiO₂ layer 85 b, and the mask material layer 2 c that are positionedhigher than the SiO₂ layer 101 are removed. Subsequently, an ionimplantation process is used to form a P⁺ layer 103 in the top portionof the Si pillar 3 c. Subsequently, a SiO₂ layer 104 is formed over thewhole structure. Subsequently, a contact hole 105 a is formed so as toextend from the upper surface of the SiO₂ layer 104 to the upper surfaceof the WSi layer 77; a contact hole 105 b is formed so as to extend fromthe upper surface of the SiO₂ layer 104 to the upper surface of the P⁺layer 103; a contact hole 105 c is formed so as to extend from the uppersurface of the SiO₂ layer 104 to the upper surface of the TiN layer 84a, and so as to be in contact with the NiSi layer 100; and a contacthole 105 d is formed so as to extend from the upper surface of the SiO₂layer 104 to the upper surface of the NiSi layer 92, and so as to be incontact with the NiSi layer 94. Subsequently, a ground wiring metallayer VSS is formed so as to connect through the contact hole 105 a tothe WSi layer 77; a power supply wiring metal layer VDD is formed so asto connect through the contact hole 105 b to the P⁺ layer 103; an inputwiring metal layer VIN is formed so as to connect through the contacthole 105 c to the TiN layer 84 a and the NiSi layer 100; and an outputwiring metal layer VOUT is formed so as to connect through the contacthole 105 d to the NiSi layers 92 and 94. As a result, a double-stackedSGT is formed in the Si pillar 3 c in which the Si substrate 1 e and thelower SGT are isolated from each other by the SiO₂ layer 72, and theupper and lower SGTs are isolated from each other by the SiO₂ layer 82.

The production method according to the fifth embodiment provides thefollowing advantages.

1. The SiO₂ layer 72, which is present in the bottom portion of the Sipillar 3 c and has, in the upper and lower regions, the recessedportions 72 a and 72 b, prevents the Si pillar 3 c from collapsing insteps after formation of the Si pillar 3 c, and eliminates the necessityof performing the step of forming an N well or a P well as in the firstembodiment. This enables a reduction in the costs.

2. The SiO₂ layer 82, which is disposed between the upper and lowerSGTs, has, in its upper and lower regions, the recessed portions 82 aand 82 b. This prevents the Si pillar 3 c from collapsing in thesubsequent steps.

Sixth Embodiment

Hereinafter, with reference to FIG. 6AA to FIG. 6CC, a method forproducing an SGT according to a sixth embodiment of the presentinvention will be described. Among FIG. 6AA to FIG. 6CC, figuressuffixed with A are plan views; figures suffixed with B are sectionalstructural views taken along lines X-X′ in the corresponding figuressuffixed with A; and figures suffixed with C are sectional structuralviews taken along lines Y-Y′ in the corresponding figures suffixed withA. The production method according to the sixth embodiment is the sameas in the steps according to the first embodiment illustrated in FIG.1AA to FIG. 1KC except for the following differences.

The same steps as in FIG. 1AA to FIG. 1DC are performed. However, themask material layers 2 and 4 may be formed of a material not providingthe function of an oxidation-resistant mask as long as they function asetching masks. Subsequently, as illustrated in FIGS. 6AA to 6AC, a maskmaterial layer 106 constituted by a SiO₂ layer, a silicon nitride(Si₃N₄) layer, and a SiO₂ layer is deposited over the whole structure.The mask material layer 106 may be formed of a material that does notprovide the function of an etching mask as long as it functions as anoxidation-resistant mask. Subsequently, a resist layer 107 is formed ina region around the Si-pillar base part 5 so as to have an upper surfacepositioned at a level lower than the upper surface of the Si-pillar basepart 5.

Subsequently, as illustrated in FIGS. 6BA to 6BC, the same process as inFIGS. 1GA to 1GC and FIGS. 2DA to 2DC is performed, to etch the maskmaterial layer 106 that is in contact with the resist layer 107, to forma mask material layer 106 a having a lower end positioned on the upperportion of the Si-pillar base part 5. Alternatively, another process maybe performed as long as it achieves exposure of the bottom portion ofthe Si-pillar base part 5.

Subsequently, as illustrated in FIGS. 6CA to 6CC, the mask materiallayer 106 a is used as an oxidation-resistant mask and the bottomportion of the Si-pillar base part 5 and the upper surface of the Sisubstrate 1a in a region around the Si-pillar base part 5 are oxidizedto form a SiO₂ layer 107. This forms, in plan view, recessed portions107 a and 107 b in the upper and lower regions of the SiO₂ layer 107under the Si pillar 3. Subsequently, the mask material layer 106 a isremoved. Subsequently, the same steps as in FIG. 1EA to FIG. 1KC areperformed to form an SGT on the Si substrate 1 a as in FIGS. 2FA to 2FC.

The production method according to the sixth embodiment provides thefollowing advantages.

1. In this embodiment, the SiO₂ layer 107, which has, in its upper andlower regions, the recessed portions 107 a and 107 b, is formed in theSi-pillar base part 5, which has a larger diameter than the Si pillar 3.The interface between the Si pillar 3 and the SiO₂ layer 107 is presentwithin the Si-pillar base part 5 having a large diameter, so that the Sipillar 3 is less likely to collapse in the subsequent steps.

2. The SiO₂ layer 107 is formed so as to extend through the whole bottomportion of the Si-pillar base part 5 to the surface layer of the Sisubstrate 1 a. As a result, the resultant SGT is insulated by the SiO₂layer 107 from the Si substrate 1 a. This means, as in the firstembodiment, elimination of the necessity of use of SOI substrates andelimination of the necessity of formation of P wells and N wells duringformation of SGT-including CMOS circuits. This enables a considerablereduction in the production costs.

3. In the first embodiment, the mask material layers 2 and 4 have bothof the function of an etching mask and the function of anoxidation-resistant mask. By contrast, in this embodiment, the maskmaterial layers 2 and 4 may have the function of an etching mask alone.This increases the degree of freedom of selecting materials for the maskmaterial layers 2, 4, and 106 a.

Seventh Embodiment

Hereinafter, with reference to FIG. 7AA to FIG. 7BC, a method forproducing an SGT according to a seventh embodiment of the presentinvention will be described. Among FIG. 7AA to FIG. 7BC, figuressuffixed with A are plan views; figures suffixed with B are sectionalstructural views taken along lines X-X′ in the corresponding figuressuffixed with A; and figures suffixed with C are sectional structuralviews taken along lines Y-Y′ in the corresponding figures suffixed withA. The production method according to the seventh embodiment is the sameas in the steps according to the first embodiment illustrated in FIG.1AA to FIG. 1KC except for the following differences.

As illustrated in FIGS. 7AA to 7AC, in the step illustrated in FIGS. 1GAto 1GC in the first embodiment, a Si₃N₄ layer 12 a is formed so as tocover the whole exposed surface of the SiO₂ layer 10. The Si₃N₄ layer 12a, a HfO₂ layer 13 a, a TiN layer 14 a, and a SiO₂ layer 15 a are formedby the processes illustrated in FIG. 1FA to FIG. 1GC. In this step, HFions are diffused through the resist layer 16, to etch off the SiO₂layer 15 that is in contact with the resist layer 16.

Subsequently, as illustrated in FIGS. 7BA to 7BC, a NiSi layer 19 acontaining a donor impurity is formed so as to surround the Si pillar 3.In this case, a Ni layer (not shown) is formed over or under a poly-Silayer containing a donor impurity (not shown) so as to be disposed, inplan view, in a region around the SiO₂ layer 15 a; subsequently, a heattreatment is performed such that the poly-Si layer is turned intosilicide and its inner side surfaces protrude to be in contact with theside surface of the Si pillar 3, to thereby form a NiSi layer 19 aa.Subsequently, a heat treatment is performed to make the donor impuritywithin the NiSi layer 19 a diffuse into the Si pillar 3 to form an N⁺layer 20 aa. In this case, the whole exposed surfaces of the SiO₂ layer10 in the region around the Si pillar 3 are covered by the Si₃N₄ layer12 a having a smaller diffusion coefficient for the donor impurity thanthe SiO₂ layer 10; as a result, diffusion of the donor impurity withinthe NiSi layer 19 a into the Si₃N₄ layer 12 a is suppressed, to therebyform a high-concentration N⁺ layer 20 aa within the Si pillar 3. In thiscase, the Si₃N₄ layer 12 a has both of a function of an etching blocklayer against the resist layer 16 containing HF ions, and a function ofa barrier insulating layer that prevents diffusion of the donor impurityfrom the NiSi layer 19 aa. Subsequently, the steps in FIG. 1IA to FIG.1KC are performed to thereby form an SGT disposed on the Si substrate 1a, and isolated from the Si substrate 1 a by the SiO₂ layer 10.

The production method according to the seventh embodiment provides thefollowing advantages.

1. In FIGS. 1HA to 1HC in the first embodiment, the top portion of theSiO₂ layer 10 is not covered by the Si₃N₄ layer 12 and is in contactwith the NiSi layer 19. A heat treatment performed in this state causesthe donor impurity within the NiSi layer 19 to diffuse into the Sipillar 3, and to diffuse also into the SiO₂ layer 10 but in a smalleramount than into the Si pillar. The SiO₂ layer 10's effect of drawingthe donor impurity from the NiSi layer 19 causes a decrease in the donorimpurity concentration of the N⁺ layer 20. This results in an increasein the series resistance of the source or drain of the SGT, which isdegradation of transistor characteristics of the SGT. By contrast, inthis embodiment, the Si₃N₄ layer 12 a is formed so as to cover the wholeexposed surfaces of the SiO₂ layer 10, so that the SiO₂ layer 10 is notin contact with the NiSi layer 19 aa. The Si₃N₄ layer 12 a functions asa barrier layer against the SiO₂ layer 10's effect of drawing the donorimpurity from the NiSi layer 19 a. This prevents the decrease in thedonor impurity concentration in the N⁺ layer 20 aa. This prevents theincrease in the series resistance of the source or drain of the SGT, andthe resultant degradation of the transistor characteristics of the SGT.

2. The Si₃N₄ layer 12 a has, in addition to the function of a barrierlayer, another function of an etching block layer against the resistlayer 16 containing HF ions. Thus, the Si₃N₄ layer 12 a preventsdegradation of the transistor characteristics of the SGT, andfacilitates formation of the NiSi layer 19 aa, which is a wiringconductor layer connecting to the N⁺ layer 20 aa.

Eighth Embodiment

Hereinafter, with reference to FIG. 8AA to FIG. 8BC, a method forproducing an SGT according to an eighth embodiment of the presentinvention will be described. Among FIG. 8AA to FIG. 8BC, figuressuffixed with A are plan views; figures suffixed with B are sectionalstructural views taken along lines X-X′ in the corresponding figuressuffixed with A; and figures suffixed with C are sectional structuralviews taken along lines Y-Y′ in the corresponding figures suffixed withA. The production method according to the eighth embodiment is the sameas in the steps according to the first embodiment illustrated in FIG.1AA to FIG. 1KC except for the following differences.

As illustrated in FIGS. 8AA to 8AC, in the step illustrated in FIGS. 1JAto 1JC of the first embodiment, before formation of the N⁺ layer 25, aSiO₂ layer 24 a is formed on the SiO₂ layer 24 disposed in a regionaround the Si pillar 3, and on the upper end portions of the HfO₂ layer13 a, the TiN layer 14 a, and the SiO₂ layer 15 a.

Subsequently, as illustrated in FIGS. 8BA to 8BC, in the stepillustrated in FIGS. 1KA to 1KC of the first embodiment, the contactholes 28 a, 28 b, and 28 c are formed; subsequently, on the bottomportions of the contact holes and the SiO₂ layer 27, a Ni layer (notshown) is formed by vapor deposition, for example. Subsequently, a heattreatment is performed to form, in the bottom portion of the Si pillar3, silicide from the NiSi layer 19 into the Si pillar 3 to thereby form,within the Si pillar 3, a NiSi layer 20 b and an N⁺ layer 20 a due tothe donor impurity pushed out from the NiSi layer 20 b. Similarly,silicide is formed between the Ni layer formed in the bottom portion ofthe contact hole 28 b and Si in the top portion of the Si pillar 3, tothereby form, in the top portion of the Si pillar 3, a NiSi layer 25 band an N⁺ layer 25 a due to the donor impurity pushed out from the NiSilayer 25 b. Subsequently, the Ni layer on the SiO₂ layer 27 is removed.Subsequently, as in the first embodiment, the wiring metal layers MS,MD, and MG are formed. Incidentally, in plan view, the whole Si pillar 3is turned into silicide to form the NiSi layers 20 b and 25 b.

Alternatively, instead of the NiSi layer 19, a layer of a materialhaving a higher silicide formation temperature than NiSi, such as atungsten silicide (WSi) layer, may be employed, so that the heattreatment performed in the step to the formation of the NiSi layer 25 bdoes not cause excessive formation of silicide into the Si pillar 3.

The production method according to the eighth embodiment provides thefollowing advantages.

As illustrated in FIGS. 8BA to 8BC, in the final step, the NiSi layer 20b is formed between the bottom portion of the Si pillar 3 and the SiO₂layer 10. In general, stacked layers having different stresscoefficients tend to separate from each other. By contrast, in thisembodiment, the recessed portions bond together the Si pillar 3 and theNiSi layer 20 b, and the NiSi layer 20 b and the SiO₂ layer 10, so thatseparation is less likely to occur. Instead of the NiSi layer 19 in thelower portion, a layer of a material having a higher silicide formationtemperature (for example, a WSi layer) than the NiSi layer 25 b in theupper portion may be employed, so that formation of silicide, whichcauses separation of the Si pillar 3, is achieved while the Si pillar 3is surrounded by support elements such as the Si₃N₄ layer 21 and theSiO₂ layer 24. This enables a further decrease in the probability ofseparation during the production. Incidentally, the structure of thisembodiment and the production method for this structure are alsoapplicable to other embodiments.

The first, second, third, sixth, seventh, and eighth embodiments havebeen described with examples of single-SGTs. The fourth and fifthembodiments have been described with examples of SGT-including CMOSinverter circuits. However, these configurations described in theembodiments are also applicable to, instead of the single-SGTs or CMOSinverter circuits, other SGT-including circuits.

The first embodiment has been described with the example in which thefirst mask material layer 2 has a bilayer structure of a Si₃N₄ layer anda SiO₂ layer. Alternatively, another structure may be employed in whicha thin SiO₂ layer is disposed between a Si₃N₄ layer and a Si substrate.The first mask material layer 2 may be constituted by a single or plurallayers of other materials as long as it has the function of an etchingmask during etching of the Si substrate 1, and the function of anoxidation-resistant mask during oxidation for forming the SiO₂ layer 10.The same applies to other embodiments according to the presentinvention.

The first embodiment has been described with the example in which thesecond mask material layer 4 has a trilayer structure constituted by aSiO₂ layer, a Si₃N₄ layer, and a SiO₂ layer. Alternatively, the secondmask material layer 4 may be constituted by a single or plural layers ofother materials as long as it has the function of an etching mask duringetching of the Si substrate 1 a, and the function of anoxidation-resistant mask during oxidation for forming the SiO₂ layer 10.The same applies to other embodiments according to the presentinvention.

In the first embodiment, in the step illustrated in FIGS. 1FA to 1FC,the mask material layer 4 is completely removed. Alternatively, the SiO₂layer constituting the mask material layer 4 may be left on the sidesurface of the Si pillar 3, and this SiO₂ layer may be used as aprotective film to prevent contamination of the surface of the Si pillar3 during formation of the Si₃N₄ layer 12. Alternatively, beforeformation of the Si₃N₄ layer 12, for example, an ALD process may beperformed such that a SiO₂ layer or a thin insulating material layer notetched by HF ions is formed so as to cover the whole structure, and thelayer is removed after formation of the Si₃N₄ layer 12, to therebyprevent contamination of the surface of the Si pillar 3 during formationof the Si₃N₄ layer 12. The same applies to other embodiments accordingto the present invention.

In the first embodiment, in the step illustrated in FIGS. 1GA to 1GC, HFgas is fed to the whole structure; and heating or the like is performedto generate HF ions and to diffuse the HF ions through the resist layer16, to thereby etch the SiO₂ layer 15 that is in contact with the resistlayer 16. However, instead of this process, another process may beemployed as long as it enables exposure of the Si surface of the bottomportion of the Si pillar 3. Alternatively, instead of feeding HF gas tothe resist layer 16, a resist layer 16 or another material layer formedso as to contain HF ions may be used for exposing the Si surface of thebottom portion of the Si pillar 3. The same applies to other embodimentsaccording to the present invention.

The second embodiment has been described with the example in which themask material layer has a trilayer structure constituted by the SiO₂layer 32 a, the Si₃N₄ layer 33 a, and the SiO₂ layer 34 a.Alternatively, the mask material layer may be constituted by a single orplural layers of other materials as long as it has the function of anoxidation-resistant mask during oxidation for forming the SiO₂ layer 36.

In FIGS. 1GA to 1GC, at least one of the SiO₂ layer 15 a and the TiNlayer 14 a is used as a mask and the HfO₂ layer 13 is etched to form theHfO₂ layer 13 a; and the exposed surface layer of the TiN layer 14 a isoxidized to form the titanium oxide (TiO) layer 17. This formation ofthe TiO layer 17 may be performed before etching of the HfO₂ layer 13 a.Another process may be performed to form an insulating layer on the endsurface of the TiO layer 17. The same applies to other embodimentsaccording to the present invention.

In the second embodiment, before formation of the oxidation-resistantmask including the SiO₂ layer 32 a, the Si₃N₄ layer 33 a, and the SiO₂layer 34 a, the mask material layer 4 is removed. Alternatively, themask material layer 4 may be left. Alternatively, the mask materiallayer 2 may be removed.

In the third embodiment, the height Lh of the SiO₂ layer 2 b is changed,to thereby obtain a desired diameter Ld (in plan view) of the Si-pillarbase part 31 a surrounding the Si pillar 3 a. Alternatively, the heightof the Si₃N₄ layer 2 a, or both of the height of the Si₃N₄ layer 2 a andthe height of the SiO₂ layer 2 b may be changed, to thereby obtain adesired diameter Ld of the Si-pillar base part 31 a.

In the third embodiment, as illustrated in FIGS. 3DA to 3DC, in order toremove the SiO₂ layer 2 b, a Si₃N₄ layer (not shown) and a SiO₂ layer(not shown) are deposited over the whole structure, and subsequently aCMP (Chemical Mechanical Polishing) process is performed to polish thewhole structure down to the level of the upper surface of the Si₃N₄layer 2 a, to thereby form the Si₃N₄ layer 39 and the SiO₂ layer 40.Instead of this process of removing the SiO₂ layer 2 b, another processmay be employed as long as it achieves removal of the SiO₂ layer 2 b.Alternatively, when the SiO₂ layer 2 b has a height Lh that does notcause a problem such as collapse of the Si pillar 3 a, the SiO₂ layer 2b is not necessarily removed. In this case, the same step as in thefirst embodiment may be employed to obtain a desired diameter Ld of theSi-pillar base part.

In the sixth embodiment, as illustrated in FIGS. 6AA to 6AC, the maskmaterial layer 106 constituted by a SiO₂ layer, a Si₃N₄ layer, and aSiO₂ layer is deposited over the whole structure. Alternatively, themask material layer 106 may be constituted by a single or plural layersof other materials as long as it has the function of anoxidation-resistant mask against oxidation for forming the SiO₂ layer107.

The second and sixth embodiments have a feature of leaving the topportions of the Si-pillar base parts 31 and 5 on the SiO₂ layers 36 and107. In these left top portions of the Si-pillar base parts 31 and 5,impurity regions containing donor or acceptor impurity atoms and servingas the source or drain of the SGTs may be formed in contact with the Sipillars 3 a and 3. In this case, it is no longer necessary to form theNiSi layer 19 and the N⁺ layer 20 in FIGS. 2FA to 2FC. The source wiringmetal layers MS are formed so as to connect, through the contact holesformed above the left top portions of the Si-pillar base parts 31 and 5,to the impurity regions in the left top portions of the Si-pillar baseparts 31 and 5. Over or within the left top portions of the Si-pillarbase parts 31 and 5, a single or plural semiconductor layers containingmetal, alloy, or donor or acceptor impurity atoms may be formed. It isobvious that the same applies to formation of other circuits includingCMOS inverter circuits.

The first embodiment has been described with the case where the firstmask material layer 2 is circular in plan view; however, the first maskmaterial layer 2 may be rectangular or elliptical. The same applies toother embodiments according to the present invention.

The first embodiment has been described with the example in which asingle Si pillar 3 is formed on the Si-pillar base part 4.Alternatively, a plurality of Si-pillar base parts and Si pillars may beformed on the Si substrate 1 a to form an SGT circuit. In this case, aSi base part that continuously extends between the Si-pillar bases isformed; on this Si base part, a SiO₂ layer 10 is formed and a SiO₂ layeris formed. Subsequently, on this SiO₂ layer, wiring conductor layers ofSGTs can be formed. The fourth embodiment has been described with theexample in which two Si pillars 3 ba and 3 bb are arranged on theSi-pillar base part 41. Alternatively, three or more Si pillars may bearranged on the Si-pillar base part 41. On a Si substrate, SGTsaccording to the first embodiment and the fourth embodiment may beformed in combination. Not only in the case where Si pillars arearranged in a straight line, but also in cases where Si pillars arearranged in another configuration such as an L shape or a T shape, aplurality of Si pillars may be arranged on the Si-pillar base part 41.The same applies to other embodiments according to the presentinvention.

In the first embodiment, the N⁺ layer 20 is formed at the stageillustrated in FIGS. 1IA to 1IC. Alternatively, this N⁺ layer 20 may beformed by the end of the steps for producing the SGT circuit. In a casewhere, instead of the NiSi layer 19, a single-crystal semiconductorlayer containing a donor or acceptor impurity is formed, thesingle-crystal semiconductor layer itself serves as a source-or-drainimpurity layer; thus, the N⁺ layer 20 may be omitted or may be formed asa thin surface layer on the side surface of the Si pillar 3. The N⁺layer 20 may be formed on the outer circumferential side surface of theSi pillar 3, or may be formed so as to occupy the whole section in planview. The same applies to other embodiments according to the presentinvention.

The vertical NAND-type flash memory circuit includes a plurality ofmemory cells stacked in the vertical direction, the plurality of memorycells each including a semiconductor pillar as the channel andincluding, around the semiconductor pillar, a tunnel oxide layer, acharge storage layer, an interlayer insulating layer, and a controlconductor layer. Semiconductor pillars at both ends of the memory cellsinclude a source line impurity layer corresponding to a source and a bitline impurity layer corresponding to a drain. In addition, when one ofmemory cells on both sides of a memory cell functions as a source, theother functions as a drain. Thus, the vertical NAND-type flash memorycircuit is one of SGT circuits. Therefore, the present invention is alsoapplicable to NAND-type flash memory circuits.

The present invention is also applicable to an SGT imaging device (forexample, refer to U.S. Pat. No. 8,748,938) including, in the bottomportion of a semiconductor pillar, an impurity region for reading signalcharges; a gate insulating layer and a gate conductor layer disposed incontact with the reading impurity region and surrounding, an uppersemiconductor pillar serving as the channel, the channel semiconductorpillar; a light-sensitive region disposed in the semiconductor pillar soas to be in contact with the upper portion of the channel; and animpurity region serving as a signal charge accumulation portion in theouter peripheral portion of the light-sensitive region.

In the first embodiment, a single SGT is formed in the Si pillar 3. Inthe fifth embodiment, two SGTs are formed in the Si pillar 3 c. Thepresent invention is also applicable to formation of a circuit in whichthree or more SGTs are formed in a Si pillar. The same applies to otherembodiments according to the present invention.

The first embodiment has been described with the Si₃N₄ layers 12 and 21,which are single-material layers. Alternatively, composite-materiallayers may be used, for example, composite-material layers having a SiO₂layer as a lower layer and a Si₃N₄ layer as an upper layer.Alternatively, instead of the Si₃N₄ layers 12 and 21, insulatingmaterial layers having small HF-ion diffusion coefficients may be used.The NiSi layers 19 and 22 may be formed by, instead of the HF ionetching process used in the first embodiment, another process. The sameapplies to other embodiments according to the present invention.

In the seventh embodiment, the NiSi layer 19 aa contains a donorimpurity. Alternatively, the NiSi layer 19 aa may contain an acceptorimpurity. In the seventh embodiment, the Si₃N₄ layer 12 a covering theexposed surface of the SiO₂ layer 10 is used as a barrier layer forprotecting the SiO₂ layer 10 from the impurity diffusing from the NiSilayer 19 aa. Instead of the Si₃N₄ layer 12 a, another material layer maybe used that has a smaller diffusion coefficient for the impuritycontained in the NiSi layer 19 aa than the SiO₂ layer 10. In the case offorming, on the SiO₂ layer 10, in addition to the Si pillar 3 having, inits lower portion, an N⁺ layer containing a donor impurity, another Sipillar having, in its lower portion, a layer containing another impuritydifferent from the impurity (for example, a P⁺ layer), it is necessaryto form a NiSi layer containing the different impurity (for example, anacceptor impurity) in addition to the NiSi layer 19 aa; a single barrierlayer protects the SiO₂ layer 10 from the impurities diffusing from bothof the NiSi layers. In this case, the barrier layer is preferably amaterial layer having smaller diffusion coefficients for both of theimpurities than the SiO₂ layer 10. Similarly, in the case of forming aplurality of Si pillars on the SiO₂ layer 10, a material layer that hassmaller diffusion coefficients for all the impurities contained in theimpurity layers formed in the lower portions of the Si pillars than theSiO₂ layer 10 may be used as a common barrier layer. In the case ofemploying, instead of the Si pillar 3, another semiconductor pillar, theSiO₂ layer 10 is preferably replaced by another insulating layer such asan oxide insulating layer of the semiconductor. In this case, thebarrier layer is formed as a material layer that has a smaller diffusioncoefficient for the impurity contained in the NiSi layer 19 aa than theinsulating layer. This barrier layer is formed between a wiring materiallayer (the NiSi layer 19 aa in the seventh embodiment) and an oxideinsulating layer (the SiO₂ layer 10 in the seventh embodiment) tothereby provide the same advantages as in the seventh embodiment. Thesame applies to other embodiments according to the present invention.

In the seventh embodiment, the Ni layer (not shown) is formed over orunder the poly-Si layer (not shown) containing a donor impurity so as tobe disposed, in plan view, in a region around the SiO₂ layer 15 a;subsequently, a heat treatment is performed to turn the poly-Si layerinto silicide such that its inner side surfaces protrude to and incontact with the side surface of the Si pillar 3 to thereby form theNiSi layer 19 aa. This process of forming the NiSi layer is alsoapplicable to other embodiments according to the present invention.

In the seventh embodiment, the Si₃N₄ layer 12 a has a function of abarrier layer against diffusion of the impurity from the NiSi layer 19aa to the SiO₂ layer 10, and a function of an etching block layeragainst etching by HF ions contained in the resist layer 16.Alternatively, the Si₃N₄ layer 12 a may be replaced by another materiallayer that has a function of a barrier layer against diffusion of theimpurity to the SiO₂ layer 10, and a function of an etching block layeragainst etching by HF ions contained in the resist layer 16.Alternatively, in the case of employing another etching process notusing HF ions, the SiO₂ layer 15 a and the Si₃N₄ layer 12 a arepreferably replaced by material layers suitable for the etching process.The same is also applicable to other embodiments according to thepresent invention.

The above-described embodiments have been described with examples inwhich the semiconductor regions such as the channel, the source, and thedrain in the semiconductor pillar are formed of Si (silicon). However,this is not limiting, and the technical idea of the present invention isalso applicable to pillar-shaped semiconductor devices in which aSi-containing semiconductor material such as SiGe or a non-Sisemiconductor material is partially or entirely employed.

In the first embodiment, the gate conductive layer is constituted by theTiN layer 14 a. However, this is not limiting, and the gate conductivelayer may be formed of another metal material. The gate conductive layermay have a multilayer structure constituted by a metal layer and, forexample, a poly-Si layer. The same is similarly applicable to otherembodiments according to the present invention.

In the first embodiment, the TiN gate conductor layer is formed by thegate first process; alternatively, the TiN gate conductor layer may beformed by the gate last process. The same is similarly applicable toother embodiments according to the present invention.

The first embodiment has been described with the SGT in which the N⁺layers 20 and 21 serving as the source and the drain are constituted byimpurity layers containing the same donor impurity. Alternatively, atunnel effect SGT may be provided in which one of the layers is an N⁺layer and the other is a P⁺ layer. The same is similarly applicable toother embodiments according to the present invention.

The fifth embodiment has been described with the example in which thegate conductor layers of the SGTs formed in the upper and lower portionsof the Si pillar 3 c are formed as layers of the same material that arethe TiN layers 84 a and 84 b. Alternatively, in the case of an N-channelSGT and a P-channel SGT, the gate conductive layers may be formed ofdifferent materials. The same is also applicable to other embodimentsaccording to the present invention.

In the eighth embodiment, the NiSi layers 20 b and 25 b and the N⁺layers 20 a and 25 a, which are alloy layers formed in upper and lowerportions of the Si pillar, may be replaced by other alloy layers thatcontain semiconductor atoms, metal atoms, and a donor or acceptorimpurity. The combinations of semiconductor atoms, metal atoms, and adonor or acceptor impurity contained in the upper and lower alloy layersmay be different between the upper and lower alloy layers. The same issimilarly applicable to other embodiments according to the presentinvention.

In the eighth embodiment, the contact hole 28 b is formed in the uppersurface of the Si pillar 3; alternatively, the contact hole 28 b may beformed so as to surround the top portion of the Si pillar 3 and have abottom portion on the SiO₂ layer 24 a, and, subsequently, the exposedtop portion of the Si pillar 3 may be covered with a Ni layer and a heattreatment may be performed to form a NiSi layer 25 b and an N⁺ layer 25a. In this case, the SiO₂ layer 24 a is preferably replaced by a layer,such as a Si₃N₄ layer, that provides a strong etching block effectduring formation of the contact hole 28 b within the SiO₂ layer 27.Alternatively, another material layer may be used that similarlyprovides the etching block effect. The same is similarly applicable toother embodiments according to the present invention.

In the eighth embodiment, the NiSi layer 25 b and the N⁺ layer 25 a maybe formed by the following process: a contact hole 28 b is formed on theSiO₂ layer 24 a so as to have an outer periphery surrounding the Sipillar 3 in plan view and have a larger width than the Si pillar 3; aNiSi layer containing a donor impurity is formed within the contact holeso as to cover at least the side surface of the top portion of the Sipillar 3; and heating is performed to form a NiSi layer 25 b in the topportion of the Si pillar 3 and to form an N⁺ layer 25 a due to diffusionof the donor impurity pushed out from the NiSi layer 25 b. The NiSilayer containing a donor impurity may be replaced by an alloy layer thatcontains a donor or acceptor impurity, metal atoms, and semiconductoratoms that are different from the semiconductor atoms constituting thesemiconductor pillar. In this case, instead of the NiSi layer 25 b, analloy layer containing the metal atoms and semiconductor atomsconstituting the semiconductor pillar is formed. Incidentally, thisalloy layer may contain the above-described semiconductor atomsdifferent from the semiconductor atoms constituting the semiconductorpillar. The descriptions in this paragraph are similarly applicable toother embodiments according to the present invention.

In the eighth embodiment, in order to form the NiSi layer 20 b and theN⁺ layer 20 a, the NiSi layer 19 containing a donor impurity is used;alternatively, a metal layer containing a donor or acceptor impurity ora material layer that contains a donor or acceptor impurity and metaland that substantially does not contain semiconductor atoms may be used.The same is also applicable to the above-described formation of the NiSilayer 25 b and the N⁺ layer 25 a from the NiSi layer containing a donorimpurity. The same is similarly applicable to other embodimentsaccording to the present invention.

In the first embodiment, the N⁺ layers 20 and 25 are formed so as to bein contact with the top and bottom of the Si pillar 3 and formed of thesame Si material as in the Si pillar 3; alternatively, the impuritylayers may be formed of another semiconductor material. In the firstembodiment, as illustrated in FIGS. 1HA to 1HC, the N⁺ layer 20 isformed in the following manner: the nickel silicide (NiSi) layer 19containing, for example, a donor impurity is formed on the Si₃N₄ layer12 so as to surround the Si pillar 3; subsequently, a heat treatment isperformed to diffuse the donor impurity from the NiSi layer 19 into theSi pillar 3. Such a material source containing an impurity is notlimited to the NiSi layer, and may be an alloy of another material, or asemiconductor layer. The N⁺ layer 20 may be formed in the followingmanner: a Ni layer is formed over or under a poly-Si layer containing adonor impurity; subsequently, a heat treatment is performed to formsilicide during which the donor impurity is diffused from the NiSi layer19 into the Si pillar 3. Instead of the Ni layer, another metal layer(for example, Co or W) may be employed. Another process may be employedto form an impurity layer so as to be in contact with the lower portionof the Si pillar 3. The same is also applicable to other embodimentsaccording to the present invention.

The first embodiment has been described with the example in which themask material layer 4 is formed on the side surface of the Si pillar 3;the mask material layer 4 may be left on the side surface or the uppersurface of the mask material layer 2. The mask material layer 4 coversthe whole side surface of the Si pillar 3. The mask material layer 4 maybe formed in the following manner: a mask material film is formed by aCVD process so as to cover the entirety of Si pillar 3; the wholestructure is then etched by an RIE process so as to leave the maskmaterial layer 4 on the side surface of the Si pillar 3. Alternatively,the mask material layer 4 may be formed in the following manner: a maskmaterial film is deposited over the whole structure; subsequently, thefilm is planarized by a CMP process so as to have a top portionpositioned at the level of the upper surface of the mask material layer2; subsequently, an RIE process is performed to etch-back the maskmaterial film down to the top portion of the Si pillar 3; subsequently,the second mask material layer is formed so as to surround the maskmaterial layer 2; subsequently, the mask material film is etched by anRIE process through the second mask material layer serving as mask. Themask material layer 4 may be formed by another process. The same is alsoapplicable to other embodiments according to the present invention.

In the first embodiment, the Si pillar 3 is formed directly on therecessed portion; alternatively, at least one other layer may be formedbetween the Si pillar 3 and the recessed portion, the at least one otherlayer each having a recessed portion in the upper region and aprotruding portion in the lower region. The same is also applicable toother embodiments according to the present invention.

The present invention encompasses various embodiments and variousmodifications without departing from the broad spirit and scope of thepresent invention. The above-described embodiments are provided forunderstanding of examples of the present invention and do not limit thescope of the present invention. Features of the above-described examplesand modifications can be appropriately combined. The above-describedembodiments from which some optional features have been eliminateddepending on the need still fall within the spirit and scope of thepresent invention.

Methods for producing a pillar-shaped semiconductor device according tothe present invention provide, at lower costs, semiconductor deviceshaving high degrees of integration.

1. A method for producing a pillar-shaped semiconductor device includinga semiconductor pillar, first and second impurity regions in contactwith lower and upper portions of the semiconductor pillar, a gateinsulating layer surrounding the semiconductor pillar between the firstand second impurity regions in a vertical direction, and a gateconductor layer surrounding the gate insulating layer, the methodcomprising: forming the semiconductor pillar on a semiconductorsubstrate; forming a first material layer surrounding the semiconductorpillar; etching the semiconductor substrate using the first materiallayer as a mask to form a semiconductor-pillar base part under thesemiconductor pillar, the semiconductor-pillar base part surrounding thesemiconductor pillar in plan view; forming a second material layercovering an upper portion of the semiconductor-pillar base part and thefirst material layer; and forming an oxidation-layer base part at alower portion of the semiconductor base part by oxidizing thesemiconductor substrate and a lower portion of the semiconductor-pillarbase part using the second material layer as an oxidation-resistantmask; wherein the semiconductor pillar is positioned within theoxidation-layer base part in plan view, and an upper surface of theoxidation-layer base part is located lower than an upper surface of thesemiconductor-pillar base part along a vertical direction.
 2. The methodfor producing a pillar-shaped semiconductor device according to claim 1,further comprising: forming a first mask material layer on thesemiconductor substrate, etching the semiconductor substrate through thefirst mask material layer serving as an etching mask to form thesemiconductor pillar, forming a second mask material layer surrounding aside surface of the semiconductor pillar, and etching the semiconductorsubstrate through the first mask material layer and the second maskmaterial layer serving as etching masks to form the semiconductor-pillarbase part under the semiconductor pillar.
 3. The method for producing apillar-shaped semiconductor device according to claim 2, furthercomprising: independently forming the first mask material layer and thesecond mask material layer as a single layer of a material providing afunction of an etching mask and a function of an oxidation-resistantmask, or each independently formed as a plurality of layers including,in their outermost portion, the single layer, wherein the first maskmaterial layer and the second mask material layer constitute theoxidation-resistant mask.
 4. The method for producing a pillar-shapedsemiconductor device according to claim 2, further comprises: forming athird-mask-material-layer by forming the oxidation-resistant mask so asto surround the semiconductor pillar with none of or at least one of thefirst mask material layer and the second mask material layer disposedbetween the oxidation-resistant mask and the semiconductor pillar, andso as to surround an upper side surface of the semiconductor-pillar basepart.
 5. The method for producing a pillar-shaped semiconductor deviceaccording to claim 4, further comprising removing the first maskmaterial layer or removing the second mask material layer, or removingboth the first mask material layer and the second mask material layer.6. The method for producing a pillar-shaped semiconductor deviceaccording to claim 4, wherein forming the third-mask-material-layerincludes forming the oxidation-resistant mask so as to surround thesemiconductor pillar with the first mask material layer and the secondmask material layer between the oxidation-resistant mask and thesemiconductor pillar so as to surround the upper side surface of thesemiconductor-pillar base part.
 7. The method for producing apillar-shaped semiconductor device according to claim 2, wherein thesecond mask material layer is formed with a predetermined thickness soas to form the semiconductor-pillar base part having a predeterminedwidth in plan view.
 8. The method for producing a pillar-shapedsemiconductor device according to claim 1, further comprising: forming aplurality of the semiconductor pillars on and sharing thesemiconductor-pillar base part, and forming the second material layer soas to surround top portions and side surfaces of all the plurality ofsemiconductor pillars and a top portion of the semiconductor base part.9. The method for producing a pillar-shaped semiconductor deviceaccording to claim 8, further comprising: forming a plurality of firstmask material layers on the semiconductor substrate; etching thesemiconductor substrate through the plurality of first mask materiallayers serving as etching masks to form the plurality of semiconductorpillars; forming the second material layer so as to surround sidesurfaces of all the semiconductor pillars, and continuously extendbetween adjacent ones of the semiconductor pillars, and etching thesemiconductor substrate through the plurality of first mask materiallayers and the second mask material layer serving as etching masks, toform the semiconductor-pillar base part under and shared by theplurality of semiconductor pillars.
 10. The method for producing apillar-shaped semiconductor device according to claim 1, furthercomprising: removing a portion of the second material layer, the portionhaving a band shape having a predetermined width in a height direction,to expose a side surface of the semiconductor pillar, and using aremaining portion of the second material layer as an oxidation-resistantmask and oxidizing the exposed side surface of the semiconductor pillarto form an additional oxide insulating layer including, in its upper andlower regions, recessed portions within the semiconductor pillar.